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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. december 1995 copyright ? intel corporation, 1995 order number: 290435-005 28F008SA-L 8-mbit (1 mbit x 8) flashfile tm memory y high-density symmetrically-blocked architecture e sixteen 64-kbyte blocks y low-voltage operation e b 3.3v g 0.3v or 5.0v g 10% v cc y extended cycling capability e 10,000 block erase cycles e 160,000 block erase cycles per chip y automated byte write and block erase e command user interface e status register y system performance enhancements e ry/by y status output e erase suspend capability y high-performance read e 200 ns maximum access time y deep power-down mode e 0.20 m ai cc typical y sram-compatible write interface y hardware data protection feature e erase/write lockout during power transitions y industry standard packaging e 40-lead tsop, 44-lead psop y etox tm iii nonvolatile flash technology e 12v byte write/block erase intel's 28F008SA-L 8 mbit flashfile tm memory is the highest density nonvolatile read/write solution for solid- state storage. the 28F008SA-L's extended cycling, symmetrically-blocked architecture, fast access time, write automation and very low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. the 28F008SA-L brings new capabilities to portable computing. application and operating system software stored in resident flash memory arrays provide instant-on, rapid execute-in-place and protection from obsolescence through in-system software updates. resident software also extends system battery life and increases reliability by reducing disk drive accesses. for high-density data acquisition applications, the 28F008SA-L offers a more cost-effective and reliable alter- native to sram and battery. traditional high-density embedded applications, such as telecommunications, can take advantage of the 28F008SA-L's nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software designs. the 28F008SA-L is offered in 40-lead tsop (standard and reverse) and 44-lead psop packages. pin assign- ments simplify board layout when integrating multiple devices in a flash memory array or subsystem. this device uses an integrated command user interface and state machine for simplified block erasure and byte write. the 28F008SA-L memory map consists of 16 separately erasable 64-kbyte blocks. intel's 28F008SA-L employs advanced cmos circuitry for systems requiring low power consumption and noise immunity. its 200 ns access time provides superior performance when compared with magnetic storage media. a deep power-down mode lowers power consumption to 0.66 m w typical thru v cc , crucial in portable computing, handheld instrumentation and other low-power applications. the rp y power control input also provides absolute data protection during system power-up/down. manufactured on intel's 0.8 micron etox process, the 28F008SA-L provides the highest levels of quality, reliability and cost-effectiveness. * other brands and names are property of their respective owners.
28F008SA-L product overview the 28F008SA-L is a high-performance 8-mbit (8,388,608-bit) memory organized as 1 mbyte (1,048,576 bytes) of 8 bits each. sixteen 64-kbyte (65,536-byte) blocks are included on the 28F008SA-L. a memory map is shown in figure 6 of this specification. a block erase operation erases one of the sixteen blocks of memory in typically 2.0 seconds , independent of the remaining blocks. each block can be independently erased and written 10,000 cycles . erase suspend mode allows sys- tem software to suspend block erase to read data or execute code from any other block of the 28F008SA-L. the 28F008SA-L is available in the 40-lead tsop (thin small outline package, 1.2 mm thick) and 44- lead psop (plastic small outline) packages. pin- outs are shown in figures 2 and 4 of this specifica- tion. the command user interface serves as the inter- face between the microprocessor or microcontroller and the internal operation of the 28F008SA-L. byte write and block erase automation allow byte write and block erase operations to be execut- ed using a two-write command sequence to the command user interface. the internal write state machine (wsm) automatically executes the algo- rithms and timings necessary for byte write and block erase operations, including verifications, thereby unburdening the microprocessor or micro- controller. writing of memory data is performed in byte increments typically within 11 m s, i pp byte write and block erase currents are 10 ma typical, 30 ma maximum. v pp byte write and block erase voltage is 11.4v to 12.6v . the status register indicates the status of the wsm and when the wsm successfully completes the desired byte write or block erase operation. the ry/by y output gives an additional indicator of wsm activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for example). status polling using ry/by y mini- mizes both cpu overhead and system power con- sumption. when low, ry/by y indicates that the wsm is performing a block erase or byte write oper- ation. ry/by y high indicates that the wsm is ready for new commands, block erase is suspended or the device is in deep powerdown mode. maximum access time is 200 ns (t acc ) over the commercial temperature range (0 cto a 70 c) and over v cc supply voltage range (3.0v to 3.6v and 4.5v to 5.5v). i cc active current (cmos read) is 5 ma typical, 12 ma maximum at 5 mhz, 3.3v g 0.3v. when the ce y and rp y pins are at v cc , the i cc cmos standby mode is enabled. a deep powerdown mode is enabled when the rp y pin is at gnd, minimizing power consumption and providing write protection. i cc current in deep powerdown is 0.20 m a typical . reset time of 500 ns is required from rp y switching high until outputs are valid to read attempts. equivalently, the device has a wake time of 1 m s from rp y high until writes to the command user interface are recognized by the 28F008SA-L. with rp y at gnd, the wsm is reset and the status register is cleared. 2
28F008SA-L figure 1. block diagram 290435 1 3
28F008SA-L table 1. pin description symbol type name and function a 0 a 19 input address inputs for memory addresses. addresses are internally latched during a write cycle. dq 0 dq 7 input/output data input/outputs: inputs data and commands during command user interface write cycles; outputs data during memory array, status register and identifier read cycles. the data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. data is internally latched during a write cycle. ce y input chip enable: activates the device's control logic, input buffers, decoders, and sense amplifiers. ce y is active low; ce y high deselects the memory device and reduces power consumption to standby levels. rp y input reset/ deep powerdown: puts the device in deep powerdown mode. rp y is active low; rp y high gates normal operation. rp y also locks out block erase or byte write operations when active low, providing data protection during power transitions. rp y active resets internal automation. exit from deep powerdown sets device to read-array mode. oe y input output enable: gates the device's outputs through the data buffers during a read cycle. oe y is active low. we y input write enable: controls writes to the command user interface and array blocks. we y is active low. addresses and data are latched on the rising edge of the we y pulse. ry/by y output ready/busy y : indicates the status of the internal write state machine. when low, it indicates that the wsm is performing a block erase or byte write operation. ry/by y high indicates that the wsm is ready for new commands, block erase is suspended or the device is in deep powerdown mode. ry/by y is always active and does not float to tri-state off when the chip is deselected or data outputs are disabled. v pp block erase/byte write power supply for erasing blocks of the array or writing bytes of each block. note: with v pp k v pplmax , memory contents cannot be altered. v cc device power supply (3.3v g 0.3v, 5v g 10%) gnd ground 4
28F008SA-L standard pinout 290435 2 reverse pinout 290435 3 figure 2. tsop lead configurations 5
28F008SA-L figure 3. tsop serpentine layout note: 1. connect all v cc and gnd pins of each device to common power supply outputs. do not leave v cc or gnd inputs disconnected. 290435 4 6
28F008SA-L 290435 5 figure 4. psop lead configuration 290435 6 figure 5. 28F008SA-L array interface to intel3.3v 80l186eb embedded microprocessor 7
28F008SA-L principles of operation the 28F008SA-L includes on-chip write automation to manage write and erase functions. the write state machine allows for: 100% ttl-level control inputs; fixed power supplies during block erasure and byte write; and minimal processor overhead with ram-like interface timings. after initial device powerup, or after return from deep powerdown mode (see bus operations), the 28F008SA-L functions as a read-only memory. ma- nipulation of external memory-control pins allow ar- ray read, standby and output disable operations. both status register and intelligent identifiers can also be accessed through the command user inter- face when v pp e v ppl . this same subset of operations is also available when high voltage is applied to the v pp pin. in addi- tion, high voltage on v pp enables successful block erasure and byte writing of the device. all functions associated with altering memory contentsebyte write, block erase, status and intelligent identifiere are accessed via the command user interface and verified thru the status register. commands are written using standard microproces- sor write timings. command user interface contents serve as input to the wsm, which controls the block erase and byte write circuitry. write cycles also inter- nally latch addresses and data needed for byte write or block erase operations. with the appropriate com- mand written to the register, standard microproces- sor read timings output array data, access the intelli- gent identifier codes, or output byte write and block erase status for verification. interface software to initiate and poll progress of in- ternal byte write and block erase can be stored in any of the 28F008SA-L blocks. this code is copied to, and executed from, system ram during actual flash memory update. after successful completion of byte write and/or block erase, code/data reads from the 28F008SA-L are again possible via the read ar- ray command. erase suspend/resume capability al- lows system software to suspend block erase to read data and execute code from any other block. fffff 64-kbyte block effff f0000 64-kbyte block dffff e0000 64-kbyte block cffff d0000 64-kbyte block bffff c0000 64-byte block affff b0000 64-kbyte block 9ffff a0000 64-kbyte block 8ffff 90000 64-kbyte block 7ffff 80000 64-kbyte block 6ffff 70000 64-kbyte block 5ffff 60000 64-kbyte block 4ffff 50000 64-kbyte block 3ffff 40000 64-kbyte block 2ffff 30000 64-kbyte block 1ffff 20000 64-kbyte block 0ffff 10000 64-kbyte block 00000 figure 6. memory map command user interface and write automation an on-chip state machine controls block erase and byte write, freeing the system processor for other tasks. after receiving the erase setup and erase confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the status register and ry/by y output. byte write is similarly controlled, after destination address and expected data are supplied. the program and erase algorithms of past intel flash memories are now regulated by the state machine, including pulse repetition where required and internal verification and margining of data. 8
28F008SA-L data protection depending on the application, the system designer may choose to make the v pp power supply switcha- ble (available only when memory byte writes/block erases are required) or hardwired to v pph . when v pp e v ppl , memory contents cannot be altered. the 28F008SA-L command user interface architec- ture provides protection from unwanted byte write or block erase operations even when high voltage is applied to v pp . additionally, all functions are dis- abled whenever v cc is below the write lockout volt- age v lko , or when rp y is at v il . the 28F008SA-L accommodates either design practice and encour- ages optimization of the processor-memory inter- face. the two-step byte write/block erase command user interface write sequence provides additional soft- ware write protection. bus operation flash memory reads, erases and writes in-system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. read the 28F008SA-L has three read modes. the memo- ry can be read from any of its blocks, and informa- tion can be read from the intelligent identifier or status register. v pp can be at either v ppl or v pph . the first task is to write the appropriate read mode command to the command user interface (array, in- telligent identifier, or status register). the 28F008SA-L automatically resets to read array mode upon initial device powerup or after exit from deep powerdown. the 28F008SA-L has four control pins, two of which must be logically active to obtain data at the outputs. chip enable (ce y ) is the device selection control, and when active enables the se- lected memory device. output enable (oe y )isthe data input/output (dq 0 dq 7 ) direction control, and when active drives data from the selected memory onto the i/o bus. rp y and we y must also be at v ih . figure 10 illustrates read bus cycle waveforms. output disable with oe y at a logic-high level (v ih ), the device out- puts are disabled. output pins (dq 0 dq 7 ) are placed in a high-impedance state. standby ce y at a logic-high level (v ih ) places the 28F008SA-L in standby mode. standby operation disables much of the 28F008SA-L's circuitry and substantially reduces device power consumption. the outputs (dq 0 dq 7 ) are placed in a high-impe- dence state independent of the status of oe y .ifthe 28F008SA-L is deselected during block erase or byte write, the device will continue functioning and consuming normal active power until the operation completes. table 2. bus operations mode notes rp y ce y oe y we y a 0 v pp dq 07 ry/by y read 1, 2, 3 v ih v il v il v ih xxd out x output disable 1, 2, 3 v ih v il v ih v ih x x high z x standby 1, 2, 3 v ih v ih x x x x high z x deep powerdown 1, 2 v il x x x x x high z v oh intelligent identifier (mfr) 1, 2 v ih v il v il v ih v il x 89h v oh intelligent identifier (device) 1, 2 v ih v il v il v ih v ih x a1h v oh write 1, 2, 3, 4, 5 v ih v il v ih v il xx d in x notes: 1. refer to dc characteristics. when v pp e v ppl , memory contents can be read but not written or erased. 2. x can be v il or v ih for control pins and addresses, and v ppl or v pph for v pp . see dc characteristics for v ppl and v pph voltages. 3. ry/by y is v ol when the write state machine is executing internal block erase or byte write algorithms. it is v oh when the wsm is not busy, in erase suspend mode or deep powerdown mode. 4. command writes involving block erase or byte write are only successfully executed when v pp e v pph . 5. refer to table 3 for valid d in during a write operation. 9
28F008SA-L deep power-down the 28F008SA-L offers a deep power-down feature, entered when rp y is at v il . current draw thru v cc is 0.20 m a typical in deep powerdown mode, with current draw through v pp typically 0.1 m a. during read modes, rp y -low deselects the memory, places output drivers in a high-impedence state and turns off all internal circuits. the 28F008SA-L re- quires time t phqv (see ac characteristics-read- only operations) after return from powerdown until initial memory access outputs are valid. after this wakeup interval, normal operation is restored. the command user interface is reset to read array, and the upper 5 bits of the status register are cleared to value 10000, upon return to normal operation. during block erase or byte write modes, rp y low will abort either operation. memory contents of the block being altered are no longer valid as the data will be partially written or erased. time t phwl after rp y goes to logic-high (v ih ) is required before an- other command can be written. this use of rp y during system reset is important with automated write/erase devices. when the sys- tem come out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during write/ erase modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization would not occur because the flash memory would be providing the status information instead of array data. intel's flash memories allow proper cpu initialization fol- lowing a system reset through the use of the rp y input. in this application rp y is controlled by the same reset y signal that resets the system cpu. intelligent identifier operation the intelligent identifier operation outputs the manu- facturer code, 89h; and the device code, a2h for the 28F008SA-L. the system cpu can then auto- matically match the device with its proper block erase and byte write algorithms. the manufacturer- and device-codes are read via the command user interface. following a write of 90h to the command user interface, a read from address location 00000h outputs the manufacturer code (89h). a read from address 00001h outputs the device code (a2h). it is not necessary to have high voltage applied to v pp to read the intelligent identifiers from the command user interface. table 3. command definitions command cycles req'd bus notes first bus cycle second bus cycle operation address data operation address data read array/reset 1 1 write x ffh intelligent identifier 3 2, 3, 4 write x 90h read ia iid read status register 2 3 write x 70h read x srd clear status register 1 write x 50h erase setup/erase confirm 2 2 write ba 20h write ba d0h erase suspend/erase resume 2 write x b0h write x d0h byte write setup/write 2 2, 3, 5 write wa 40h write wa wd alternate byte write setup/write 2 2, 3, 5 write wa 10h write wa wd notes: 1. bus operations are defined in table 2. 2. ia e identifier address: 00h for manufacturer code, 01h for device code. ba e address within the block being erased. wa e address of memory location to be written. 3. srd e data read from status register. see table 4 for a description of the status register bits. wd e data to be written at location wa. data is latched on the rising edge of we y . iid e data read from intelligent identifiers. 4. following the intelligent identifier command, two read operations access manufacture and device codes. 5. either 40h or 10h are recognized by the wsm as the byte write setup command. 6. commands other than those shown above are reserved by intel for future device implementations and should not be used. 10
28F008SA-L write writes to the command user interface enable read- ing of device data and intelligent identifiers. they also control inspection and clearing of the status register. additionally, when v pp e v pph , the com- mand user interface controls block erasure and byte write. the contents of the interface register serve as input to the internal state machine. the command user interface itself does not occupy an addressable memory location. the interface reg- ister is a latch used to store the command and ad- dress and data information needed to execute the command. erase setup and erase confirm com- mands require both appropriate command data and an address within the block to be erased. the byte write setup command requires both appropriate command data and the address of the location to be written, while the byte write command consists of the data to be written and the address of the loca- tion to be written. the command user interface is written by bringing we y to a logic-low level (v il ) while ce y is low. addresses and data are latched on the rising edge of we y . standard microprocessor write timings are used. refer to ac write characteristics and the ac wave- forms for write operations, figure 11, for specific timing parameters. command definitions when v ppl is applied to the v pp pin, read opera- tions from the status register, intelligent identifiers, or array blocks are enabled. placing v pph on v pp enables successful byte write and block erase oper- ations as well. device operations are selected by writing specific commands into the command user interface. table 3 defines the 28F008SA-L commands. read array command upon initial device powerup and after exit from deep powerdown mode, the 28F008SA-L defaults to read array mode. this operation is also initiated by writing ffh into the command user interface. mi- croprocessor read cycles retrieve array data. the device remains enabled for reads until the com- mand user interface contents are altered. once the internal write state machine has started a block erase or byte write operation, the device will not rec- ognize the read array command, until the wsm has completed its operation. the read array command is functional when v pp e v ppl or v pph . intelligent identifier command the 28F008SA-L contains an intelligent identifier operation, initiated by writing 90h into the command table 4. status register definitions wsms ess es bws vpps r r r 76543210 sr.7 e write state machine status 1 e ready 0 e busy sr.6 e erase suspend status 1 e erase suspended 0 e erase in progress/completed sr.5 e erase status 1 e error in block erasure 0 e successful block erase sr.4 e byte write status 1 e error in byte write 0 e successful byte write sr.3 e v pp status 1 e v pp low detect; operation abort 0 e v pp ok sr.2sr.0 e reserved for future enhancements these bits are reserved for future use and should be masked out when polling the status register. notes: ry/by y or the write state machine status bit must first be checked to determine byte write or block erase com- pletion, before the byte write or erase status bit are checked for success. if the byte write and erase status bits are set to ``1''s during a block erase attempt, an improper command se- quence was entered. attempt the operation again. if v pp low status is detected, the status register must be cleared before another byte write or block erase opera- tion is attempted. the v pp status bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm in- terrogates the v pp level only after the byte write or block erase command sequences have been entered and in- forms the system if v pp has not been switched on. the v pp status bit is not guaranteed to report accurate feed- back between v ppl and v pph . 11
28F008SA-L user interface. following the command write, a read cycle from address 00000h retrieves the manufac- turer code of 89h. a read cycle from address 00001h returns the device code of a1h. to termi- nate the operation, it is necessary to write another valid command into the register. like the read array command, the intelligent identifier command is func- tional when v pp e v ppl or v pph . read status register command the 28F008SA-L contains a status register which may be read to determine when a byte write or block erase operation is complete, and whether that oper- ation completed successfully. the status register may be read at any time by writing the read status register command (70h) to the command user in- terface. after writing this command, all subsequent read operations output data from the status regis- ter, until another valid command is written to the command user interface. the contents of the status register are latched on the falling edge of oe y or ce y , whichever occurs last in the read cy- cle. oe y or ce y must be toggled to v ih before further reads to update the status register latch. the read status register command functions when v pp e v ppl or v pph . clear status register command the erase status and byte write status bits are set to ``1''s by the write state machine and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 4). by allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or eras- ing multiple blocks in sequence). the status regis- ter may then be polled to determine if an error oc- curred during that sequence. this adds flexibility to the way the device may be used. additionally, the v pp status bit (sr.3) must be re- set by system software before further byte writes or block erases are attempted. to clear the status register, the clear status register command (50h) is written to the command user interface. the clear status register command is functional when v pp e v ppl or v pph . erase setup/erase confirm commands erase is executed one block at a time, initiated by a two-cycle command sequence. an erase setup command (20h) is first written to the command user interface, followed by the erase confirm command (d0h). these commands require both appropriate sequencing and an address within the block to be erased to ffh. block preconditioning, erase and verify are all handled internally by the write state machine, invisible to the system. after the two-com- mand erase sequence is written to it, the 28F008SA-L automatically outputs status register data when read (see figure 8; block erase flowchart). the cpu can detect the completion of the erase event by analyzing the output of the ry/by y pin, or the wsm status bit of the status register. when erase is completed, the erase status bit should be checked. if erase error is detected, the status register should be cleared. the command user interface remains in read status register mode until further commands are issued to it. this two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. also, reliable block erasure can only occur when v pp e v pph . in the absence of this high voltage, memory contents are protected against era- sure. if block erase is attempted while v pp e v ppl , the v pp status bit will be set to ``1''. erase attempts while v ppl k v pp k v pph produce spurious results and should not be attempted. erase suspend/erase resume commands the erase suspend command allows block erase interruption in order to read data from another block of memory. once the erase process starts, writing the erase suspend command (b0h) to the com- mand user interface requests that the wsm sus- pend the erase sequence at a predetermined point in the erase algorithm. the 28F008SA-L continues to output status register data when read, after the erase suspend command is written to it. polling the wsm status and erase suspend status bits will de- termine when the erase operation has been sus- pended (both will be set to ``1''). ry/by y will also transition to v oh . at this point, a read array command can be written to the command user interface to read data from blocks other than that which is suspended. the only other valid commands at this time are read status register (70h) and erase resume (d0h), at which time the wsm will continue with the erase process. the erase suspend status and wsm status bits of the status register will be automatically cleared and ry/by y will return to v ol . after the erase resume command is written to it, the 28F008SA-L automati- cally outputs status register data when read (see figure 9; erase suspend/resume flowchart). v pp must remain at v pph while the 28F008SA-L is in erase suspend. 12
28F008SA-L byte write setup/write commands (40h or 10h) byte write is executed by a two-command sequence. the byte write setup command (40h or 10h) is writ- ten to the command user interface, followed by a second write specifying the address and data (latched on the rising edge of we y ) to be written. the wsm then takes over, controlling the byte write and write verify algorithms internally. after the two- command byte write sequence is written to it, the 28F008SA-L automatically outputs status register data when read (see figure 7; byte write flowchart). the cpu can detect the completion of the byte write event by analyzing the output of the ry/by y pin, or the wsm status bit of the status register. only the read status register command is valid while byte write is active. when byte write is complete, the byte write status bit should be checked. if byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for ``1''s that do not successfully write to ``0''s. the command user in- terface remains in read status register mode until further commands are issued to it. if byte write is attempted while v pp e v ppl , the v pp status bit will be set to ``1''. byte write attempts while v ppl k v pp k v pph produce spurious results and should not be attempted. extended block erase/byte write cycling intel has designed extended cycling capability into its etox flash memory technologies. the 28F008SA-L is designed for 10,000 byte write/block erase cycles on each of the sixteen 64-kbyte blocks. low electric fields, advanced oxides and minimal oxide area per cell subjected to the tunnel- ing electric field combine to greatly reduce oxide stress and the probability of failure. a 20-mbyte sol- id-state drive using an array of 28F008SA-Ls has a mtbf (mean time between failure) of 3.33 million hours (1) , over 60 times more reliable than equivalent rotating disk technology. automated byte write the 28F008SA-L integrates the quick-pulse pro- gramming algorithm of prior intel flash memory de- vices on-chip, using the command user interface, status register and write state machine (wsm). on-chip integration dramatically simplifies system software and provides processor interface timings to the command user interface and status register. wsm operation, internal verify and v pp high voltage presence are monitored and reported via the ry/by y output and appropriate status register bits. figure 7 shows a system software flowchart for device byte write. the entire sequence is performed with v pp at v pph . byte write abort occurs when rp y transitions to v il ,orv pp drops to v ppl . although the wsm is halted, byte data is partially written at the location where byte write was aborted. block era- sure, or a repeat of byte write, is required to initialize this data to a known value. automated block erase as above, the quick-erase algorithm of prior intel flash devices is now implemented internally, includ- ing all preconditioning of block data. wsm opera- tion, erase success and v pp high voltage presence are monitored and reported through ry/by y and the status register. additionally, if a command other than erase confirm is written to the device following erase setup, both the erase status and byte write status bits will be set to ``1''s. when issuing the erase setup and erase confirm commands, they should be written to an address within the address range of the block to be erased. figure 8 shows a system software flowchart for block erase. erase typically takes 2.0 seconds per block. the erase suspend/erase resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed. a system software flowchart is shown in figure 9. the entire sequence is performed with v pp at v pph . abort occurs when rp y transitions to v il or v pp falls to v ppl , while erase is in progress. block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. design considerations three-line output control the 28F008SA-L will often be used in large memory arrays. intel provides three control inputs to accom- modate multiple memory connections. three-line control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur to efficiently use these control inputs, an address decoder should enable ce y , while oe y should be connected to all memory devices and the system's read y control line. this assures that only selected memory devices have active outputs while deselect- ed memory devices are in standby mode. rp y should be connected to the system powergood sig- nal to prevent unintended writes during system pow- er transitions. powergood should also toggle during system reset. (1) assumptions: 10-kbyte file written every 10 minutes. (20-mbyte array)/(10-kbyte file) e 2,000 file writes before erase required. (2000 files writes/erase) c (10,000 cycles per 28F008SA-L block) e 20 million file writes. (20 c 10 6 file writes) c (10 min/write) c (1 hr/60 min) e 3.33 c 10 6 mtbf . 13
28F008SA-L ry/by y and byte write/block erase polling ry/by y is a full cmos output that provides a hard- ware method of detecting byte write and block erase completion. it transitions low time t whrl after a write or erase command sequence is written to the 28F008SA-L, and returns to v oh when the wsm has finished executing the internal algorithm. ry/by y can be connected to the interrupt input of the system cpu or controller. it is active at all times, not tristated if the 28F008SA-L ce y or oe y inputs are brought to v ih . ry/by y is also v oh when the device is in erase suspend or deep powerdown modes. 290435 13 bus command comments operation write byte write data e 40h (10h) setup address e byte to be written write byte write data to be written address e byte to be written standby/read check ry/by y v oh e ready, v ol e busy or read status register check sr.7 1 e ready, 0 e busy toggle oe y or ce y to update status register repeat for subsequent bytes full status check can be done after each byte or after a sequence of bytes write ffh after the last byte write operation to reset the device to ready array mode full status check procedure 290435 14 bus command comments operation optional cpu may already have read status register data in wsm read ready polling above standby check sr.3 1 e v pp low detect standby check sr.4 1 e byte write error sr.3 must be cleared, if set during a byte write attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple bytes are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 7. automated byte write flowchart 14
28F008SA-L 290435 15 bus command comments operation write erase data e 20h setup address e within block to be erased write erase data e d0h address e within block to be erased standby/read check ry/by y v oh e ready, v ol e busy or read status register check sr.7 1 e ready, 0 e busy toggle oe y or ce y to update status register repeat for subsequent bytes full status check can be done after each block or after a sequence of blocks write ffh after the last block erase operation to reset the device to ready array mode full status check procedure 290435 16 bus command comments operation optional cpu may already have read status register data in wsm read ready polling above standby check sr.3 1 e v pp low detect standby check sr.4,5 both 1 e command sequence error standby check sr.5 1 e block erase error sr.3 must be cleared, if set during a block erase attempt, before further attempts are allowed by the write state machine sr.5 is only cleared by the clear status register command, in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 8. automated block erase flowchart 15
28F008SA-L 290435 17 bus command comments operation write erase data e b0h suspend write read data e 70h status register standby/ check ry/by y read v oh e ready, v ol e busy or read status register check sr.7 1 e ready, 0 e busy toggle oe y or ce y to update status register standby check sr.6 1 e suspended write read array data e ffh read read array data from block other than that being erased. write erase resume data e d0h figure 9. erase suspend/resume flowchart power supply decoupling flash memory power switching characteristics re- quire careful device decoupling. system designers are interested in 3 supply current issues; standby current levels (i sb ), active current levels (i cc ) and transient peaks produced by falling and rising edges of ce y . transient current magnitudes depend on the device outputs' capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 m f ceramic capacitor connected between each v cc and gnd, and be- tween its v pp and gnd. these high frequency, low inherent-inductance capacitors should be placed as close as possible to package leads. additionally, for every 8 devices, a 4.7 m f electrolytic capacitor should be placed at the array's power supply con- nection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductances. v pp trace on printed circuit boards writing flash memories, while they reside in the tar- get system, requires that the printed circuit board designer pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for writing and erasing. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will de- crease v pp voltage spikes and overshoots. 16
28F008SA-L v cc ,v pp ,rp y transitions and the command/status registers byte write and block erase completion are not guar- anteed if v pp drops below v pph . if the v pp status bit of the status register (sr.3) is set to ``1'', a clear status register command must be issued before further byte write/block erase attempts are allowed by the wsm. otherwise, the byte write (sr.4) or erase (sr.5) status bits of the status register will be set to ``1''s if error is detected. rp y transitions to v il during byte write and block erase also abort the operations. data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. device poweroff, or rp y transitions to v il , clear the status register to initial value 10000 for the upper 5 bits. the command user interface latches commands as issued by system software and is not altered by v pp or ce y transitions or wsm actions. its state upon powerup, after exit from deep powerdown or after v cc transitions below v lko , is read array mode. after byte write or block erase is complete, even after v pp transitions down to v ppl , the command user interface must be reset to read array mode via the read array command if access to the memory array is desired. power up/down protection the 28F008SA-L is designed to offer protection against accidental block erasure or byte writing dur- ing power transitions. upon power-up, the 28F008SA-L is indifferent as to which power supply, v pp or v cc , powers up first. power supply sequenc- ing is not required. internal circuitry in the 28F008SA-L ensures that the command user inter- face is reset to the read array mode on power up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we y and ce y must be low for a command write, driving either to v ih will inhibit writes. the command user interface architecture provides an added level of protection since altera- tion of memory contents only occurs after success- ful completion of the two-step command sequences. finally, the device is disabled until rp y is brought to v ih , regardless of the state of its control inputs. this provides an additional level of memory protection. power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash nonvolatility increases us- able battery life, because the 28F008SA-L does not consume any power to retain code or data when the system is off. in addition, the 28F008SA-L's deep powerdown mode ensures extremely low power dissipation even when system power is applied. for example, porta- ble pcs and other power sensitive applications, us- ing an array of 28F008SA-Ls for solid-state storage, can lower rp y to v il in standby or sleep modes, producing negligable power consumption. if access to the 28F008SA-L is again needed, the part can again be read, following the t phqv and t phwl wake- up cycles required after rp y is first raised back to v ih . see ac characteristicseread-only and write operations and figures 10 and 11 for more informa- tion. 17
28F008SA-L absolute maximum ratings * operating temperature during read b 20 cto a 70 c (1) during block erase/byte write 0 cto a 70 c temperature under bias b 20 cto a 80 c storage temperature b 65 cto a 125 c voltage on any pin (except v cc and v pp ) with respect to gnd b 2.0v to a 7.0v (2) v pp program voltage with respect to gnd during block erase/byte write b 2.0v to a 14.0v (2, 3) v cc supply voltage with respect to gnd b 2.0v to a 7.0v (2) output short circuit current100 ma (4) notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is b 0.5v on input/output pins. during transitions, this level may undershoot to b 2.0v for periods k 20 ns. maximum dc voltage on input/output pins is v cc a 0.5v which, during transitions, may overshoot to v cc a 2.0v for periods k 20 ns. 3. maximum dc voltage on v pp may overshoot to a 14.0v for periods k 20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. ac specifications are valid at both voltage ranges. see dc characteristics for voltage range specific specification. operating conditions symbol parameter notes min max unit t a operating temperature b 20 70 c v cc v cc supply voltage 5 3.00 3.60 v v cc v cc supply voltage 5 4.50 5.50 v dc characteristics v cc e 3.3v g 0.3v read, 3.0 3.6 program/erase symbol parameter notes min typ max unit test condition i li input load current 1 g 0.5 m av cc e v cc max v in e v cc or gnd i lo output leakage current 1 g 0.5 m av cc e v cc max v out e v cc or gnd i ccs v cc standby current 1, 3 1.0 2.0 ma v cc e v cc max ce y e rp y e v ih 30 100 m av cc e v cc max ce y e rp y e v cc g 0.2v i ccd v cc deep powerdown 1 0.20 1.2 m arp y e gnd g 0.2v current i out (ry/by y ) e 0ma 18
28F008SA-L dc characteristics (continued) symbol parameter notes min typ max unit test condition i ccr v cc read current 1 5 12 ma v cc e v cc max, ce y e gnd f e 5 mhz, i out e 0ma cmos inputs 512mav cc e v cc max, ce y e v il f e 5 mhz, i out e 0ma ttl inputs i ccw v cc byte write current 1 6 18 ma byte write in progress i cce v cc block erase current 1 6 18 ma block erase in progress i cces v cc erase suspend 1, 2 3 6 ma block erase suspended current ce y e v ih i pps v pp standby current 1 g 1 g 15 m av pp s v cc i ppd v pp deep powerdown 1 0.10 5.0 m arp y e gnd g 0.2v current i ppr v pp read current 200 m av pp l v cc i ppw v pp byte write current 1 10 30 ma v pp e v pph byte write in progress i ppe v pp block erase current 1 10 30 ma v pp e v pph block erase in progress i ppes v pp erase suspend 1 90 200 m av pp e v pph current block erase suspended v il input low voltage b 0.5 0.6 v v ih input high voltage 2.0 v cc a 0.5 v v ol output low voltage 3 0.4 v v cc e v cc min, i ol e 2ma v oh1 output high voltage (ttl) 3 2.4 v v cc e v cc min, i oh eb 2ma v oh2 output high voltage 0.85 v cc vi oh e 2.5 m a, v cc e v cc min (cmos) v cc b 0.4 i oh eb 100 m a, v cc e v cc min v ppl v pp during normal 4 0.0 6.5 v operations v pph v pp during erase/write 11.4 12.0 12.6 v operations v lko v cc erase/write lock 2.0 v voltage capacitance (5) t a e 25 c, f e 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in e 0v c out output capacitance 8 12 pf v out e 0v 19
28F008SA-L notes: 1. all currents are in rms unless otherwise noted. typical values at v cc e 3.3v, v pp e 12.0v, t e 25 c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the 28F008SA-L is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. includes ry/by y . 4. block erases/byte writes are inhibited when v pp e v ppl and not guaranteed in the range between v pph and v ppl . 5. sampled, not 100% tested. dc characteristics v cc e 5.0v g 10% symbol parameter notes min typ max unit test condition i li input load current 1 g 1.0 m av cc e v cc max v in e v cc or gnd i lo output leakage current 1 g 10 m av cc e v cc max v out e v cc or gnd i ccs v cc standby current 1, 3 1.0 2.0 ma v cc e v cc max ce y e rp y e v ih 30 100 m av cc e v cc max ce y e rp y e v cc g 0.2v i ccd v cc deep powerdown 1 0.20 1.2 m arp y e gnd g 0.2v current i out (ry/by y ) e 0ma i ccr v cc read current 1 20 35 ma v cc e v cc max, ce y e gnd f e 5 mhz, i out e 0ma cmos inputs 25 50 ma v cc e v cc max, ce y e v il f e 5 mhz, i out e 0ma ttl inputs i ccw v cc byte write current 1 10 30 ma byte write in progress i cce v cc block erase current 1 10 30 ma block erase in progress i cces v cc erase suspend 1, 2 5 10 ma block erase suspended, current ce y e v ih i pps v pp standby current 1 g 1 g 15 m av pp s v cc i ppd v pp deep powerdown 1 0.10 5.0 m arp y e gnd g 0.2v current i ppr v pp read current 1 90 200 m av pp l v cc i ppw v pp byte write current 1 10 30 ma v pp e v pph byte write in progress i ppe v pp block erase current 1 10 30 ma v pp e v pph block erase in progress i ppes v pp erase suspend 1 90 200 m av pp e v pph current block erase suspended v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ol output low voltage 3 0.45 v v cc e v cc min, i ol e 5.8 ma v oh1 output high voltage (ttl) 3 2.4 v v cc e v cc min, i oh eb 2.5 ma v oh2 output high voltage 0.85 v cc vi oh eb 2.5 m a, v cc e v cc min (cmos) v cc b 0.4 i oh eb 100 m a, v cc e v cc min v ppl v pp during normal 4 0.0 6.5 v operations 20
28F008SA-L dc characteristics (continued) v cc e 5.0v g 10% symbol parameter notes min typ max unit test condition v pph v pp during erase/write 11.4 12.0 12.6 v operations v lko v cc erase/write lock 2.0 v voltage notes: 1. all currents are in rms unless otherwise noted. typical values at v cc e 5.0v, v pp e 12.0v, t e 25 c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the 28F008SA-L is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. includes ry/by y . 4. block erases/byte writes are inhibited when v pp e v ppl and not guaranteed in the range between v pph and v ppl . ac input/output reference waveform 290435 7 ac test inputs are driven at 3.0v for a logic ``1'' and 0.0v for a logic ``0''. input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) k 10 ns. ac testing load circuit (2) c l e 50 pf c l includes jig 290435 8 capacitance r l e 3.3 k x ac characteristicseread-only operations (1) v cc e 3.3v g 0.3v, 5.0v g 10% versions 28f008sa-150 unit symbol parameter notes min max t avav t rc read cycle time 150 ns t avqv t acc address to output delay 150 ns t elqv t ce ce y to output delay 2 150 ns t phqv t pwh rp y high to output delay 600 ns t glqv t oe oe y to output delay 2 75 ns t elqx t lz ce y to output low z 3 0 ns t ehqz t hz ce y high to output high z 3 55 ns t glqx t olz oe y to output low z 3 0 ns t ghqz t df oe y high to output high z 3 30 ns t oh output hold from addresses, ce y or oe y 30 ns change, whichever is first notes: 1. see ac input/output reference waveform for timing measurements. 2. oe y may be delayed up to t ce t oe after the falling edge of ce y without impact on t ce . 3. sampled, not 100% tested. 21
28F008SA-L figure 10. ac waveform for read operations 290435 9 22
28F008SA-L ac characteristicsewrite operations (1) v cc e 3.3v g 0.3v, 5.0v g 10% versions 28F008SA-L200 unit symbol parameter notes min max t avav t wc write cycle time 200 ns t phwl t ps rp y high recovery to we y going low 2 1 m s t elwl t cs ce y setup to we y going low 20 ns t wlwh t wp we y pulse width 60 ns t vpwh t vps v pp setup to we y going high 2 100 ns t avwh t as address setup to we y going high 3 60 ns t dvwh t ds data setup to we y going high 4 60 ns t whdx t dh data hold from we y high 5 ns t whax t ah address hold from we y high 5 ns t wheh t ch ce y hold from we y high 10 ns t whwl t wph we y pulse width high 30 ns t whrl we y high to ry/by y going low 100 ns t whqv1 duration of byte write operation 5, 6 6 m s t whqv2 duration of block erase operation 5, 6 0.3 sec t whgl write recovery 0 m s before read t qvvl t vph v pp hold from valid srd, ry/by y high 2, 6 0 ns notes: 1. read timing characteristics during erase and byte write operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in for byte write or block erasure. 4. refer to table 3 for valid d in for byte write or block erasure. 5. the on-chip write state machine incorporates all byte write and block erase system functions and overhead of standard intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. byte write and block erase durations are measured to completion (sr.7 e 1, ry/by y e v oh ). v pp should be held at v pph until determination of byte write/block erase success (sr.3/4/5 e 0) 23
28F008SA-L block erase and byte write performance v cc e 3.3v to 0.3v, 5.0v g 10% parameter notes 28F008SA-L-200 unit min typ (1) max block erase time 2 2.0 12.5 sec block write time 2 0.7 2.6 sec byte write time 8 (note 3) m s notes: 1. 25 c, 12.0 v pp . 2. excludes system-level overhead. 3. contact your intel representative for information on the maximum byte write specification. 24
28F008SA-L figure 11. ac waveform for write operations 290435 10 25
28F008SA-L alternative ce y -controlled writes v cc e 3.3v g 0.3v, 5.0v g 10% versions 28F008SA-L200 unit symbol parameter notes min max t avav t wc write cycle time 200 ns t phel t ps rp y high recovery to ce y going low 2 1 m s t wlel t ws we y setup to ce y going low 0 ns t eleh t cp ce y pulse width 70 ns t vpeh t vps v pp setup to ce y going high 2 100 ns t aveh t as address setup to ce y going high 3 60 ns t dveh t ds data setup to ce y going high 4 60 ns t ehdx t dh data hold from ce y high 5 ns t ehax t ah address hold from ce y high 5 ns t ehwh t wh we y hold from ce y high 0 ns t ehel t eph ce y pulse width high 25 ns t ehrl ce y high to ry/by y going low 100 ns t ehqv1 duration of byte write operation 5 6 m s t ehqv2 duration of block erase operation 5 0.3 sec t ehgl write recovery before read 0 m s t qvvl t vph v pp hold from valid srd, ry/by y high 2, 5 0 ns notes: 1. chip-enable controlled writes: write operations are driven by the valid combination of ce y and we y . in systems where ce y defines the write pulsewidth (within a longer we y timing waveform), all setup, hold and inactive we y times should be measured relative to the ce y waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in for byte write or block erasure. 4. refer to table 3 for valid d in for byte write or block erasure. 5. byte write and block erase durations are measured to completion (sr.7 e 1, ry/by y e v oh ). v pp should be held at v pph until determination of byte write/block erase success (sr.3/4/5 e 0) 26
28F008SA-L figure 12. alternate ac waveform for write operations 290435 11 27
28F008SA-L ordering information 290435 12 valid combinations: e28F008SA-L200 f28F008SA-L200 pa28F008SA-L200 additional information references order number 28f008sa datasheet 290429 28f008sa 8 mbit (1mbit x 8) flash memory smartdie tm product specification 271296 ap-359 ``28f008sa hardware interfacing'' 292094 ap-360 ``28f008sa software drivers'' 292095 ap-364 ``28f008sa automation and algorithms'' 292099 er-27 ``the intel 28f008sa flash memory'' 294011 er-28 ``etox tm iii flash memory technology'' 290412 revision history number description 002 modified erase suspend flowchart lowered v lko from 2.2v to 2.0v combined v pp standby current and v pp read current into one v pp standby current spec. with two test conditions (dc characteristics table) removed e250 speed bin 003 pwd renamed to rp y for jedec standardization compatibility. changed i pps standby current specifications from g 10 m ato g 15 m a in dc characteristics tables. 004 changed i ccr test condition from f e 8 mhz to f e 5 mhz changed i ccs max spec. from 50 m a to 2.0 ma added i ppr spec. corrected i pps spec. typo added v ohz (output high voltageecmos) spec. changed operating temp range (read) from 0 c70 cto b 20 c70 c. changed v cc range from 3.3v g 0.3v to 3.15v 3.6v for program/erase. added byte write time spec. 005 changed intelligent identifier device code from a1h to a2h v cc supply voltage (program/erase) is now the same as read i ccd max changed to 1.2 m a ac characteristicseread-only operation: t avav e 150 ns, t avqv e 150 ns, t elqv e 150 ns, t phqv e 600 ns, t glqv e 75 ns corrected i ccs typical value to read 1.0. 28

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